Principal Engineer, Verification

About this Position:

Define and develop verification architecture and verification plan

Define and develop verification methodologies

Define and develop verification environments

Write verification specifications, verification plans, and documentation

Develop test bench and automatic regression plans for a complex SoC

Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs (schematics, analog, RTL)

Complete block-level verification and chip level verification

Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges

Able to work mostly independently and handle complex SoC Verification platform

Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities

Mentor Junior Engineers on need basis

Job Requirements

Required Skills and Experience:

10+ years related proven silicon design or verification work experience

Hands on project experience with leading edge verification methodologies like OVM/UVM

Domain experience of DDR3/DDR4/LPDDR3/LPDDR4 is must

Hands on project experience in verifying projects using DDR2/DDR3 protocols

Hands on project experience in coverage/assertion driven verification

Knowledge of IC chip design, development flow, process, and methodology

Knowledge of CMOS logic design, circuit design, and circuit analysis

Proficient in HDL languages SystemVerilog, Verilog and VHDL

Good knowledge of UNIX shell scripting, Perl and TCL scripting.

Proven experience in writing verification plans and test bench development , simulation, and debugging

Proficient with UNIX environment, and CAE/CAD tools such as schematic capture, simulation, design verification

Good analytical and problem solving skills

Excellent written and verbal communication in English.

Willingness to lead small d teams