Principal Verification Engineer

Job Description

To play the role of Verification engineer at the Block level, Chip level Functional verification.

Develop verification test plans from design specifications.

Development of test environments using System Verilog and UVM verification methodologies.

Integration with RTL and basic simulation bring-up for the design.

Create multiple test cases as per test plan and launch regressions.

Generate Code/Functional coverage, analyze coverage results and correlate with the test plan.

Working the design team members to identify and quickly resolve problems with the design.

Support cross functional teams such as FPGA emulation, ASIC validation on testing, debug and bring up of ASIC devices.

Communicate regularly with the team members to resolve issues and report status.

Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges.

Job Requirement

Bachelor’s/Master’s degree in Electrical / Electronic Engineering or equivalent.

Domain Expertise : AHB, AXI, PCIE, USB2.0, USB3.0, Ethernet 802.3 standard.

Languages (must): Verilog, system Verilog

Methodologies (One of them is must): OVM/UVM/VMM

EDA Tools (One of them is must): Questasim, VCS, NCSim, NCVerilog

Experience in developing Test Bench components in both block level and SOC level.

Experience in Creating test plan and Writing test sequence.

Strong in simulation and debugging skill including GLS

Functional Coverage, Code Coverage & Assertions (OVA, SVA, PSL) (Desirable)

Experience in integrating and using third party VIPs (desirable)

Scripting and programming skills using Bash, Perl, Python is a plus

Good analytical and problem-solving skills

Excellent written and verbal communication in English.

Good teamwork and time management skills, self-direction and the desire to excel in a competitive environment.